The MSP430F5529 Launchpad is a tinkerers dream! Powerful and complicated, will provide you with many happy afternoons ;) In this post we examine the UCS (Unified Clock System) and how you can use to it clock your Launchpad up to it's maximum speed.
The MSP430F5529 launchpad offers plenty of clock sources and three different clocks to work with:
- MCLK, the Master Clock - Used for the CPU. Usually fast.
- SMCLK, the Sub-Master Clock, used for peripherals. Usually fast (equal to MCLK, or a fraction of it).
- ACLK, the Auxiliary clock, usually slow and used for peripherals when very low power is needed.
And what do you feed to these clocks?
- VLOCLK: On-chip, very low frequency oscillator. Around 10 KHz and not accurate at all!
- REFOCLK: Reference oscillator at the usual 32768 Hz (the common RTC frequency). Medium accuracy, again provided on chip.
- DCO: Digitally Controlled Oscillator. On chip, fast oscillator source.
- XT1: Onboard crystal at 32768 Hz (like REFOCLK but more accurate, since it is a crystal).
- XT2: Onboard crystal at 4 MHz.
The above sources can be combined in a bewildering number of ways: different sources to different clocks, divided by a number of dividers or used to synthesize and fine tune the DCO up to the 25MHz maximum clock of the F5529.
Let's see how we can use and set these using the DriverLib (part of MSPWare) provided by TI.
Important Note: TI has changed some function names in the recent version of MSPWare. To follow our examples download the latest CCS (Code Composer Studio) and MSPWare (I've tried to show the differences in the listings).
Initial Investigation
#include "driverlib.h"
uint32_t mclk = 0;
uint32_t smclk = 0;
uint32_t aclk = 0;
int main(void) {
WDT_A_hold(WDT_A_BASE);
aclk=UCS_getACLK();
mclk=UCS_getMCLK();
smclk=UCS_getSMCLK();
while (1);
return (0);
}
And the results are:
- MCLK: 1048576 Hz (1 MHz)
- SMCLK: Same as MCLK
- ACLK: 32768 Hz
If you never touched your launchpad clocks, you are only running at 1 MHz. We can do a lot better than that!
Setting Clocks using Internal Clock Sources (the simple way)
can use some simple functions to change any of the clocks using them as sources. For example, setting the ACLK to use the REFOCLK:
#include "driverlib.h"
void initClocks();
uint32_t mclk = 0;
uint32_t smclk = 0;
uint32_t aclk = 0;
int main(void) {
WDT_A_hold(WDT_A_BASE);
initClocks();
aclk=UCS_getACLK();
mclk=UCS_getMCLK();
smclk=UCS_getSMCLK();
while (1);
return (0);
}
void initClocks(){
UCS_initClockSignal( // clockSignalInit in previous driverlib
UCS_ACLK, // Set the auxiliary clock, using the
UCS_REFOCLK_SELECT, // reference oscillator (32768 Hz) and
UCS_CLOCK_DIVIDER_2 // divide it by this value.
);
}
Using a divider of 2, yields an ACLK frequency of 16384. You are welcome to try other values for the divider (in powers of 2 up to 32) as well as trying to set MCLK and SMCLK the same way (just substitute UCS_ACLK with UCS_MCLK or UCS_SMCLK). The syntax is no different with VLOCLK (from now on we only show different versions of the initClocks function):
void initClocks(){
UCS_initClockSignal(
UCS_ACLK,
UCS_VLOCLK_SELECT,
UCS_CLOCK_DIVIDER_32
);
}
With a clock divider of 32, we can go as low as 312 Hz!
Using the Crystals - The easy way
void initClocks(){
// Important First Steps: Configure Pins for Crystals!
// All to port P5
// PIN5 -> XT1 OUT
// PIN4 -> XT1 IN
// PIN3 -> XT2 OUT
// PIN2 -> XT1 IN
GPIO_setAsPeripheralModuleFunctionInputPin(
GPIO_PORT_P5,
GPIO_PIN4+GPIO_PIN2
);
GPIO_setAsPeripheralModuleFunctionOutputPin(
GPIO_PORT_P5,
GPIO_PIN5+GPIO_PIN3
);
// YOU HAVE to inform the system of the crystal frequencies
// You probably want to use #defines for these values
UCS_setExternalClockSource(
32768, // Frequency of XT1 in Hz.
4000000 // Frequency of XT2 in Hz.
);
// Initialize the crystals
UCS_turnOnXT2( // was UCS_XT2Start in previous driverlib
UCS_XT2_DRIVE_4MHZ_8MHZ
);
UCS_turnOnLFXT1( //was UCS_LFXT1Start in previous driverlib
UCS_XT1_DRIVE_0,
UCS_XCAP_3
);
// Use the crystals to set the clocks
UCS_initClockSignal(
UCS_MCLK,
UCS_XT2CLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
UCS_initClockSignal(
UCS_SMCLK,
UCS_XT2CLK_SELECT,
UCS_CLOCK_DIVIDER_2
);
UCS_initClockSignal(
UCS_ACLK,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
}
We have just used the 4 MHz XT2 to set MCLK to 4 MHz and SMCLK to 2MHz. We also used the 32768 Hz XT1 to set ACLK. This method will allows to clock our system up to the XT2 frequency of 4MHz. To clock up to the full 25 MHz we need to set the DCO, the Digitally Controlled Oscillator.
Setting the DCO
// MCLK = Master Clock (CPU)
#define MCLK_FREQ_KHZ 4000
// Reference frequency (Frequency Locked Loop)
#define FLLREF_KHZ 32
// Ratio used to set DCO (Digitally Controlled Oscillator)
#define MCLK_FLLREF_RATIO MCLK_FREQ_KHZ/FLLREF_KHZ
Our initClocks function now looks like this:
void initClocks(){
UCS_initClockSignal(
UCS_FLLREF, // The reference for Frequency Locked Loop
UCS_REFOCLK_SELECT, // Select 32Khz reference osc
UCS_CLOCK_DIVIDER_1
);
// Start the FLL and let it settle
// This becomes the MCLCK and SMCLK automatically
UCS_initFLLSettle(
MCLK_FREQ_KHZ,
MCLK_FLLREF_RATIO
);
/* Option: Further divide the frequency obtained for DCO
UCS_initClockSignal(
UCS_MCLK,
UCS_DCOCLKDIV_SELECT,
UCS_CLOCK_DIVIDER_4
); */
// Set auxiliary clock
UCS_initClockSignal(
UCS_ACLK,
UCS_REFOCLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
}
We first initialize the FLL reference to the 32 KHz of the reference oscillator (REFOCLK). We then initialize the FLL itself and let it settle (the call returns when the FLL has acquired a stable frequency and all faults are cleared). When initFLLSettle completes, both MCLK and SMCLK are set to the frequency of the DCO. Optionally, we can use the DCOCLKDIV to set the clocks to fractions of the DCO. In a pinch, you could change just one line to speed up to 8 MHz:
#define MCLK_FREQ_KHZ 8000
Keep in mind that going to frequencies higher than 8 MHz requires you to set the core power mode. We are currently at PMM_CORE_LEVEL_0, the default core power mode. Insert this line at the top of the initClocks function:
PMM_setVCore(PMM_CORE_LEVEL_0);
and modify it according to the following table:
up to 8 MHz => PMM_CORE_LEVEL_0
up to 12 MHz => PMM_CORE_LEVEL_1
up to 20 MHz => PMM_CORE_LEVEL_2
up to 25 MHz => PMM_CORE_LEVEL_3
Not all frequencies are available at all operating voltages, but this is not a problem for Launchpad users which always run at the full 3.3V. If you try to set the frequency higher than the current core level would allow, the initFLLSettle function may never return.
We have used the on-chip reference oscillator as the source for the FLL reference. We can also use XT1 or XT2 for the same purpose.
Using XT1/XT2 as the FLL reference
Our initial defines are as follows (delete the ones defined previously if you wish to test this):
// Desired MCLK frequency
#define MCLK_FREQ_KHZ 20000
// On board crystals frequencies (in Hz)
#define XT1_FREQ 32768
#define XT2_FREQ 4000000
#define XT1_KHZ XT1_FREQ/1000
#define XT2_KHZ XT2_FREQ/1000
// Ratio used to set DCO (Digitally Controlled Oscillator)
// We are setting the FLL reference to 1 MHz (XT2/4)
// Remember to use the same divider in UCS_initClock
#define MCLK_FLLREF_RATIO MCLK_FREQ_KHZ/(XT2_KHZ/4)
Our initClocks function is now a little more involved:
void initClocks(){
// Set core power mode
PMM_setVCore(PMM_CORE_LEVEL_3);
// Connect Pins to Crystals
GPIO_setAsPeripheralModuleFunctionInputPin(
GPIO_PORT_P5,
GPIO_PIN4+GPIO_PIN2
);
GPIO_setAsPeripheralModuleFunctionOutputPin(
GPIO_PORT_P5,
GPIO_PIN5+GPIO_PIN3
);
First we set the power mode to the highest one (level 3) for 20 MHz operation.
Then we set the pins where the crystals are connected.
// Inform the system of the crystal frequencies
UCS_setExternalClockSource(
XT1_FREQ, // Frequency of XT1 in Hz.
XT2_FREQ // Frequency of XT2 in Hz.
);
// Initialize the crystals
UCS_turnOnXT2(
UCS_XT2_DRIVE_4MHZ_8MHZ
);
UCS_turnOnLFXT1(
UCS_XT1_DRIVE_0,
UCS_XCAP_3
);
We inform the system of the crystal frequencies and initialize the two crystals (For failsafe operation you are advised to check the 'WithTimeout' variants of these functions).
UCS_initClockSignal(
UCS_FLLREF, // The reference for Frequency Locked Loop
UCS_XT2CLK_SELECT, // Select XT2
UCS_CLOCK_DIVIDER_4 // FLL ref. will be 1 MHz (4MHz XT2/4)
);
We set the FLL reference frequency to 1 MHz by dividing the XT2 frequency by 4. We have already accounted for that in our MCLK_FLLREF_RATIO.
UCS_initFLLSettle(
MCLK_FREQ_KHZ,
MCLK_FLLREF_RATIO
);
We initialize the FLL and wait for it to settle. This will set the DCO (and subsequently, MCLK and SMCLK) to our desired frequency of 20 MHz. Optionally, we can set SMCLK to a lower frequency by using the DCOCLKDIV:
// Optional: set SMCLK to something else than full speed
UCS_initClockSignal(
UCS_SMCLK,
UCS_DCOCLKDIV_SELECT,
UCS_CLOCK_DIVIDER_1
);
Finally, we set the ACLK as well:
// Set auxiliary clock
UCS_initClockSignal(
UCS_ACLK,
UCS_XT1CLK_SELECT,
UCS_CLOCK_DIVIDER_1
);
}
You may download this final complete example here.
Happy programming!
